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| Data Sheet No. PD60193 IR21093(S) HALF-BRIDGE DRIVER Features * Floating channel designed for bootstrap operation * * * * * * * * * Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 10 to 20V Undervoltage lockout for both channels 3.3V, 5V and 15V input logic compatible Cross-conduction prevention logic Matched propagation delay for both channels High side output in phase with IN input Logic and power ground +/- 5V offset Internal 540ns dead-time Lower di/dt gate driver for better noise immunity Product Summary VOFFSET IO+/VOUT ton/off (typ.) Dead Time 600V max. 120 mA / 250 mA 10 - 20V 750 & 200 ns 540 ns Packages Description The IR21093(S) are high voltage, high speed power MOSFET and IGBT drivers with dependent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable rugge8-Lead SOIC 8-Lead PDIP dized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. Typical Connection up to 600V VCC VCC IN VB HO VS TO LOAD IN COM LO IR21093 (Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1 IR21093(S) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VCC VLO VIN dVS/dt PD RthJA TJ TS TL Definition High side floating absolute voltage High side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic input voltage Allowable offset supply voltage transient Package power dissipation @ TA +25C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (8 Lead PDIP) (8 Lead SOIC) (8 Lead PDIP) (8 Lead SOIC) Min. -0.3 VB - 25 VS - 0.3 -0.3 -0.3 VSS - 0.3 -- -- -- -- -- -- -50 -- Max. 625 VB + 0.3 VB + 0.3 25 VCC + 0.3 VCC + 0.3 50 1.0 0.625 125 200 150 150 300 Units V V/ns W C/W C Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential. Symbol VB VS VHO VCC VLO VIN TA Definition High side floating supply absolute voltage High side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic input voltage Ambient temperature Min. VS + 10 Note 1 VS 10 0 VSS -40 Max. VS + 20 600 VB 20 VCC VCC 125 Units V C Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-3 for more details). 2 www.irf.com IR21093(S) Dynamic Electrical Characteristics VBIAS (V CC, VBS) = 15V, CL = 1000 pF, and TA = 25C, unless otherwise specified. Symbol ton toff MT tr tf DT MDT Definition Turn-on propagation delay Turn-off propagation delay Delay matching, HS & LS turn-on/off Turn-on rise time Turn-off fall time Deadtime: LO turn-off to HO turn-on(DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime matching = DTLO - HO - DTHO-LO Min. -- -- -- -- -- 400 -- Typ. 750 200 0 150 50 540 0 Max. Units Test Conditions 950 280 70 220 80 680 60 nsec VS = 0V VS = 0V VS = 0V VS = 0V or 600V Static Electrical Characteristics VBIAS (V CC, VBS ) = 15V and TA = 25C unless otherwise specified. The VIL, VIH and IIN parameters are referenced to COM and are applicable to the respective input leads. The VO, IO and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol VIH VIL VOH VOL ILK IQBS IQCC IIN+ IINVCCUV+ VBSUV+ VCCUVVBSUVVCCUVH VBSUVH IO+ IO- Definition Logic "1" input voltage for HO & logic "0" for LO Logic "0" input voltage for HO & logic "1" for LO High level output voltage, VBIAS - VO Low level output voltage, VO Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Logic "1" input bias current Logic "0" input bias current VCC and VBS supply undervoltage positive going threshold VCC and VBS supply undervoltage negative going threshold Hysteresis Output high short circuit pulsed vurrent Output low short circuit pulsed current Min. Typ. Max. Units Test Conditions 2.9 -- -- -- -- 20 0.4 -- -- 8.0 7.4 0.3 120 250 -- -- 0.8 0.3 -- 60 1.0 5 1 8.9 8.2 0.7 200 350 -- 0.8 1.4 0.6 50 150 1.6 20 2 9.8 9.0 -- -- -- VO = 0V, PW 10 s VO = 15V,PW 10 s A mA V VCC = 10V to 20V VCC = 10V to 20V IO = 20 mA IO = 20 mA VB = VS = 600V VIN = 0V or 5V VIN = 0V or 5V RDT = 0 A IN = 5V, SD = 0V IN = 0V, SD = 5V V mA www.irf.com 3 IR21093(S) Functional Block Diagrams VB IR21093 IN VSS/COM LEVEL SHIFT HV LEVEL SHIFTER PULSE GENERATOR UV DETECT R PULSE FILTER R S Q HO VS DEADTIME UV DETECT VCC LO VSS/COM LEVEL SHIFT DELAY COM Lead Definitions Symbol Description IN VB HO VS VCC LO COM Logic input for high and low side gate driver outputs (HO and LO), in phase with HO (referenced to COM) High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return 4 www.irf.com IR21093(S) Lead Assignments 1 2 3 4 VCC IN COM LO VB HO VS 8 7 6 5 1 2 3 4 VCC IN COM LO VB HO VS 8 7 6 5 8-Lead PDIP 8-Lead SOIC IR21093 IR21093S IN(LO) IN 50% 50% IN(HO) ton HO tr 90% toff 90% tf LO LO HO Figure 1. Input/Output Timing Diagram 10% 10% Figure 2. Switching Time Waveform Definitions IN (LO) 50% 50% 50% 50% IN IN (HO) 90% LO HO 10% HO DT 10% DT LO MT 90% MT 90% 10% LO Figure 3. Deadtime Waveform Definitions HO Figure 4. Delay Matching Waveform Definitions www.irf.com 5 IR21093(S) Case Outlines 8 Lead PDIP 01-6014 01-3003 01 (MS-001AB) D A 5 B F OOT PRINT 8X 0.72 [.028] DIM A b INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 A1 .0040 c 6 E 8 7 6 5 H 0.25 [.010] A 6.46 [.255] D E e e1 H K L 8X 1.78 [.070] 1 2 3 4 .050 BAS IC .025 BAS IC .2284 .0099 .016 0 .2440 .0196 .050 8 1.27 BAS IC 0.635 BAS IC 5.80 0.25 0.40 0 6.20 0.50 1.27 8 6X e e1 A C 3X 1.27 [.050] y K x 45 y 0.10 [.004] 8X b 0.25 [.010] A1 CAB 8X L 7 8X c NOT ES: 1. DIMENS IONING & T OLERANCING PE R ASME Y14.5M-1994. 2. CONT ROLLING DIMENSION: MILLIMET ER 3. DIMENS IONS ARE SHOWN IN MILLIME TE RS [INCHES]. 4. OUT LINE CONF ORMS T O JEDEC OUTLINE MS-012AA. 5 DIMENSION DOES NOT INCLUDE MOLD PROT RUS IONS. MOLD PROTRUSIONS NOT T O E XCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROT RUS IONS. MOLD PROTRUSIONS NOT T O E XCEED 0.25 [.010]. 7 DIMENSION IS T HE LE NGTH OF LEAD FOR SOLDE RING TO A SUBS TRAT E. 8 Lead SOIC 6 01-6027 01-0021 11 (MS-012AA) 7/9/2001 www.irf.com |
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